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Job Description
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.