Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
Develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA).
Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios.
Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks.
Analyze coverage data to identify verification gaps and track progress toward tape-out milestones.

Design Verification Engineer, Silicon

Job Description