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Job Description
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Develop cross language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems. Close coverage measures to identify verification holes and to show progress towards tape-out.