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ASIC Design Verification Engineer, Compute
Sunnyvale, CA, USAPosted 4 days ago
hybrid
No longer available
Job Description
- Plan the verification of complex digital design blocks by thoroughly understanding design specification and interacting with design engineers to identify important verification scenarios.
- Build a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Analyze coverage measures to identify verification holes and to show progress towards tape-out.