Back to jobs
Job Description
- Implement DFT Register-Transfer Level (RTL) logic and validate the same. Generate and validate Automatic Test Pattern Generation (ATPG) test patterns for various SoC blocks under executive guidance.
- Implement and verify basic DFT logic like scan, MBIST, and boundary scan architectures.
- Perform gate-level simulations to verify the timing and functionality of specific test modes.
- Assist the team in post-silicon testing and debugging failure logs from Automated Test Equipment (ATE) data.
- Maintain and run automation scripts in Python or Tcl for standard DFT workflows.