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Job Description
- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.
- Develop diagnostic databases, software and hardware for logic and memory fail debug.
- Design and implement system level test strategy.
- Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT Compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.