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Job Description
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team.
- Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, path delay, and IDDQ) for Automated Test Equipment (ATE), while actively managing pattern volume and test time reduction (TTR) strategies.
- Develop and verify specialized test sequences and parametric measurement patterns to validate and characterize analog IPs (PLLs, LDOs, ADCs) and high-speed I/Os (SerDes, DDR, PCIe, MIPI).
- Partner closely with the Product Engineering teams to validate patterns on silicon, lead the diagnosis of ATE failures, and perform root-cause analysis to support yield learning and rapid ramp-to-production.
- Enhance DFT flows and methodologies using scripting (Tcl, Perl, Python) to automate insertion and validation processes, ensuring a correct-by-construction approach for future SoC.