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Job Description
- Drive early process and metal stack analysis, influencing power architecture, including unique power rails, domain boundaries, block pitch, through-silicon via plans, routing resources, and voltage budgets.
- Deliver power grid designs for all power domains and intellectual properties, meeting power density and integration requirements, including custom power grids for power-critical blocks.
- Optimize through-silicon via and power grid co-design on 3D stacked dies, ensuring design rule check cleanliness, maximize routing resources, incorporating metal-insulator-metal insertion, and augmenting power grids to improve electromigration and IR drop.
- Collaborate with clock, full-chip, physical design flow owners, and package, bump, and redistribution layer designers to co-optimize designs and accommodate top-level routes.
- Stabilize and finalize power grid designs aligned to project milestone requirements, including comprehensive design rule check clean-up.