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Job Description
- Define, develop, and optimize high-volume manufacturing (HVM) processes for advanced semiconductor packaging technologies for consumer devices, ensuring compliance with electrical, thermal, mechanical, environmental, and cost requirements, especially mobile SOC SIP for on-device AI.
- Drive process optimization and yield improvement using Design of Experiments (DOE) methodology, and establish rigorous process monitoring and control systems to ensure robust manufacturing. Establish and evaluate the effects of package assembly and bumping processes, specifically assessing Chip Package Interaction (CPI) effects such as Silicon ELK stress and impact on board-level reliability.
- Lead Electromigration (EM) evaluations for fine-pitch package solutions, defining material and process requirements to meet long-term package development and reliability roadmaps. Perform comprehensive failure analysis and root cause resolution for manufacturing and field issues encountered during both the technology development and mass production phases.
- Collaborate and manage key suppliers, including OSATs, substrate vendors, and packaging ecosystem partners, to drive technology roadmap execution and establish internal packaging.
- Domestic and International travel required.