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Job Description
- Lead the RTL design and implementation of high-speed blocks. Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
- Transform high-level architectural specifications and communication theory models into efficient, bit-exact SystemVerilog/Verilog implementations.
- Perform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.
- Drive the front-end design flow, including synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalency Checking (LEC) to ensure robust, sign-off quality designs.
- Collaborate closely with verification teams to develop bit-exact C++/SystemC models and UVM environments for comprehensive RTL verification.