ASIC Design Verification Engineer, Silicon at Google

Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
Work closely with design, architecture, software, silicon validation, back-end implementation stakeholders to make technical decisions and to come up with detailed test plans, dependencies and deliverables.
Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases ; close coverage measures to identify verification holes and to show progress towards tape-out.
Primary point of contact on functional verification to cross-functional teams and drive verification methodologies and improvements. Debug tests with design engineers to deliver functionally correct design blocks.

ASIC Design Verification Engineer, Silicon