Senior Lead Engineer - RTL

Senior Lead RTL Engineer

• Design and develop RTL (Verilog/SystemVerilog) for ASIC/SoC
• Own module-level architecture and micro-architecture definition
• Work closely with verification, synthesis, and physical design teams
• Drive RTL quality: lint, CDC, synthesis readiness
• Support integration and debug of complex SoC designs
• Mentor junior engineers and guide technical decisions
• Collaborate with global teams (India/Japan)

• Strong RTL design (Verilog/SystemVerilog)
• Good understanding of SoC architecture
• Experience with synthesis, timing basics (STA awareness)
• Debug and problem-solving skills
• Knowledge of low-power / DFT / CDC is a plus