Back to jobsBachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
3-5 years of experience in RTL design, mixed signal concepts, and verification, with a strong understanding of the entire ASIC design flow.
Strong knowledge of digital design principles, front-end tools, clock design, datapath, timing analysis of CMOS digital circuits, Verilog, SystemVerilog.
Strong knowledge of FPGA design, firmware development for test systems, and high-speed data transmission.
Working knowledge of synthesis, static timing, DFT is a plus.
Proficiency in scripting languages such as Perl, Python, or Tcl for automation.
Excellent problem-solving abilities, with a keen eye for detail and a methodical approach to debugging and optimization.
Effective communication skills, with the ability to collaborate with cross-functional teams and present technical information clearly.
Ability to adapt to new tools, technologies, and methodologies, staying current with industry trends and advancements.
Strong organizational skills, the ability to manage multiple tasks simultaneously, and a proactive approach to continuous improvement.
