Job Description
We are seeking an experienced Lead Semiconductor Packaging Engineer to work on a supplier site in Malta, NY as a full time Quantinuum employee developing innovative and reliable packaging schemes for the highly scaled ion traps in our quantum computers.
All applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.
Key Responsibilities:
- Develop and implement advanced packaging concepts for tiling large assemblies of ion trap chips, electrical chips and optical chips together
- Lead cross-functional teams to develop packaging strategies for advanced packaging concepts supporting large-format ion trap chips with high I/O signal count and density
- Generate packaging requirements for mechanical, thermal, electrical, and optical performance
- Lead a team working with vendors to implement and validate packaging processes
- Support all stages of ion trap development to ensure compatibility with packaging
- Lead a team of packaging engineers to interface with broader Quantinuum team to ensure ion trap packaging meets system requirements
- Champion engagements with 3rd parties to cultivate key partnerships, supplier relationships, and co-development opportunities
YOU MUST HAVE:
- Minimum Bachelor’s degree with 10+ years’ experience OR Master’s degree with 8+ year’s experience OR PhD with 6+ year’s experience in advanced semiconductor packaging development
- Due to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status
- Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.
WE VALUE:
- PhD in Physics or Engineering
- Experience with advanced large area multi-chip semiconductor packaging technologies
- Experience with large heterogeneous integration and 2.5-3D packaging techniques
- Experience with high-density I/O technologies
- Experience with photonic packaging and fiber-to-chip or optical chip-to-optical chip coupling
- A proven track record of innovation and IP development
- Experience working within a cross-functional team environment
Compensation & Benefits:
Incentive Eligible – Range posted is inclusive of bonus target
The pay range for this role is $152,000 - $190,000 annually. Actual compensation within this range may vary based on the candidate’s skills, educational background, professional experience, and unique qualifications for the role.
