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Job Description
- Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
- Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
- Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.