Back to jobs
Job Description
- Plan and execute the verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems.
- Close coverage measures to identify verification holes and show progress towards tape-out.