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Job Description
- Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
- Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
- Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
- Collaborate with post silicon team, Physical Design and Power Architects.
- Support the post-silicon phase to achieve final Production Release Qualification (PRQ). and Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.