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Job Description
- Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
- Participate in DFT logic insertion like scan and BIST at RTL and netlist level.
- Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
- Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support.
- Perform quality check flows like Lint, CDC, of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.