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Job Description
- Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios.
- Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs using SVA and formal tools.
- Identify and define all relevant coverage measures to address design corner-cases.
- Debug tests with design engineers to ensure functionally correct design blocks.
- Close coverage gaps to identify verification holes and demonstrate progress towards tape-out.