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Job Description
- Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
- Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
- Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
- Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
- Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.