Browse Jobs
Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
Texas Instruments
Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and
d-Matrix
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value
Pineapple Hospitality Company
Do your life’s best work here - with the whole world watching . Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The Design Verificati
9to5Mac
Do your life’s best work here - with the whole world watching . Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The Design Verificati
Apple
Do your life’s best work here - with the whole world watching . Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The Design Verificati
Pineapple Hospitality Company
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
Pineapple Hospitality Company
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
9to5Mac
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
9to5Mac
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
Apple
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
Apple
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verificat
Dahl Consulting
Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios. Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formal
Dahl Consulting
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct desig
Dahl Consulting
Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios. Work closely with design, architecture, software, s
Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios. Work closely with design, architecture, software, s
Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios. Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formal
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct desig
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Ver
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Ver
Dahl Consulting
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Ver
Dahl Consulting
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM). Identify and write all types
Dahl Consulting
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
Dahl Consulting
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Ver
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct desig
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure