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Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
981 jobs match your filters
2w
Senior CPU Design Verification Engineer, Silicon
Dahl Consulting
Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of qualit
2w
Senior CPU Design Verification Engineer, Silicon
Dahl Consulting
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
2w
Senior SoC Design Verification Engineer, Google Cloud
Dahl Consulting
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or forma
2w
ASIC Design Verification Engineer, Google Cloud
Dahl Consulting
Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verification Method
2w
Silicon Design Verification Engineer
Dahl Consulting
Plan the verification of digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios. Develop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or
Mountain View, CA, USA
hybrid
2w
ASIC Design Verification Engineer, TPU Compute
Dahl Consulting
Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verifi
2w
ASIC Design Verification Engineer, TPU Cloud
Dahl Consulting
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or for
Sunnyvale, CA, USA
hybrid
2w
Senior CPU Design Verification Engineer, Google Cloud
Dahl Consulting
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or forma
2w
Senior ASIC Design Verification Engineer, Google Cloud
Dahl Consulting
Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or for
2w
Silicon Design Verification Engineer
Dahl Consulting
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
2w
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Senior Design Verification Engineer
DEKA Research & Development
DEKA Research & Development, located in Manchester, NH, is seeking a Senior Test Engineer to work in a dynamic medical device R&D environment. This is a high visibility role with a direct impact on the success of our projects. It will be a great opportunity to work on some amazin
Manchester, NH
onsiteEasy Apply
3w
CPU Design Verification Engineer
Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that enable production of CPU’s. Verify and v
3w
Junior SOC Design Verification Engineer, Google Cloud
Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios. Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formal
3w
ASIC Design Verification Engineer, TPU
Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM,
3w
Senior Design Verification Engineer, Networking, Google Cloud
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios. Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test cover
3w
Lead CPU Design Verification Engineer, Silicon
Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of qualit
3w
Senior Design Verification Engineer, Multimedia/AI/ML, Silicon
Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process. Plan the verification of multimedia design blocks at subsystem level by understanding the
3w
CPU Design Verification Engineer
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
3w
Junior CPU Design Verification Engineer, Google Cloud
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog or formally verif
3w
Silicon Design Verification Engineer, Quantum AI
Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Develop and maintain constrained-random verification environments using System Verilog and Un
3w
ASIC Design Verification Engineer, Platforms and Devices
Plan and execute the verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems. Create and enhance constrained-random verification environments using SystemVerilog and UVM. Identify and write all types of coverage measures for stimulus
3w
ASIC Design Verification Engineer, Google Cloud
Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verification Method
3w
SoC Performance Design Verification Engineer, Silicon
Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure
3w
Senior CPU Design Verification Engineer, Silicon
Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of qualit
3w
Senior Design Verification Engineer, TPU, Google Cloud
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct desig