Job Description
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
Summary of Job:
Mixed Signal layout group involves in a wide range of layout design for analog/mixed-signal product such as driver IC, Power Supply IC, etc.
Responsibilities:
1
Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2
Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3
Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4
Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5
Where possible, use schematic driven layout and consider top level auto routing.
6
Involve in review session and prepare all related document and data preparation for wafer tape out.
Requirements:
Academic
-
Bachelor's Degree Engineering in Electrical/Electronic, Physics, Computer or related fields
Communication
1
Must have Good verbal and written communication skills in English
Japanese is a plus
Skills/Experience
1
Thorough understanding of integrated analog circuit design
2
Thorough understanding of chip layout in cell and block level creation, edit and full verification.
3
Experience with layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4
Experience in analog IC/ mixed signals IC layout designs and verifications. Able to perform with ideas on chip size reduction.
5
Highly self-motivated and adaptable.
6
Having the basic knowledge of CMOS related devices including high voltage and the skill of deciphering Design Manual.
Supplementary Requirements:
1
Layout & EDA tool skill: Expertise with Cadence and Synopsys
2
Willing to put extra effort to keep the project schedule.
3
At least have a minimum of 3-5 years’ experience in Analog IC layout design.
4
Willing to work flexible hours to support different time zone teams.
5
Willing to relocate to Malaysia or other country to support Design Team.
6
Need to work onsite.
8
Must have good verbal and written communication skills in English.
9
Good interpersonal, communication, and collaboration skills.
We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.