Senior Design Verification Engineer
Job Description
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Design Verification Engineer based in India.
This role sits at the core of advanced silicon development, focusing on verification of interconnect and chassis IP blocks that power next-generation computing systems. You will own end-to-end verification activities, from planning and test strategy to coverage closure and debug resolution, ensuring the highest levels of quality and reliability. The environment is highly technical, fast-paced, and collaborative, requiring close interaction with architecture, design, and software teams. You will build scalable, reusable verification frameworks and contribute directly to improving automation and efficiency across verification workflows. The role demands strong hands-on expertise in SystemVerilog/UVM and deep protocol understanding, along with the ability to independently drive complex verification tasks. You will also play an increasing role in mentoring junior engineers and shaping best practices. AI-assisted engineering tools are integrated into daily workflows, supporting productivity and innovation.
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Design Verification Engineer based in India.
This role sits at the core of advanced silicon development, focusing on verification of interconnect and chassis IP blocks that power next-generation computing systems. You will own end-to-end verification activities, from planning and test strategy to coverage closure and debug resolution, ensuring the highest levels of quality and reliability. The environment is highly technical, fast-paced, and collaborative, requiring close interaction with architecture, design, and software teams. You will build scalable, reusable verification frameworks and contribute directly to improving automation and efficiency across verification workflows. The role demands strong hands-on expertise in SystemVerilog/UVM and deep protocol understanding, along with the ability to independently drive complex verification tasks. You will also play an increasing role in mentoring junior engineers and shaping best practices. AI-assisted engineering tools are integrated into daily workflows, supporting productivity and innovation.