Browse Jobs
Browse fresh roles from company career pages, then filter by keyword, location, salary, skills, remote scope, and more. Each listing links back to the employer-controlled apply path when available.
212 jobs match your filters
5mo
Senior DFT Engineer
Arrow Electronics
Position: Senior DFT Engineer Job Description: Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services
6th Block Koramangala, 3rd Floor, Nos. 29&30, Garden, Bangalore- 560095, Karnātaka, India
onsite
5mo
Senior DFT Engineer
Arrow Components
Position: Senior DFT Engineer Job Description: Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services
Bangalore, India
hybridFull-time
6mo
A
Senior/Staff DFT Engineer
Axelera AI
About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-
Hybrid/Remote - Europe (incl. UK)
remoteFull-timeEasy Apply
10mo
2026 Campus - SoC DFT Engineer
NXP Semiconductors
NXP team members create breakthrough technologies that make the connected world better, safer and more secure. We're looking for innovative, passionate, and talented people like you to join our team. Responsibility: • Proficiency in whole DFT architecture definition. • S
Tianjin (Teda)
onsiteFull-time
11mo
2026 Campus - SoC DFT Engineer
NXP Semiconductors
Responsibilities: Participate in DFT feature and architecture definition for complex SOC Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic Generate DFT related timing constraints and support timing closure with backend engineer DFT test
Shanghai (Pudong)
onsiteFull-time
15mo
Senior DFT Engineer
Texas Instruments
We are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction co
Bengaluru, Karnataka, India
hybrid
25mo
Senior DFT Engineer
Cadence
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression s
Bangalore
remoteFull-time
63mo
O
Senior DFT Engineer
Omni Design Technologies
We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with rtl and pnr design team to drive testability is a key feature of this role! We are looking for an experienced DFT engineer
Bangalore
remoteFull-timeEasy Apply
2d
SoC DFT Engineer, Google Cloud
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bound
Tel-Aviv, Israel
hybrid
3d
SoC DFT Engineer, Google Cloud
Dahl Consulting
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bound
Tel-Aviv, Israel
hybrid
3d
Silicon DFT Engineer, Cloud Silicon
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, path delay, and IDDQ) for Au
3d
Junior SoC DFT Engineer, Google Cloud
Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bounda
3d
Senior Silicon DFT Engineer, Google Cloud
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs. Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG). Work with other
4d
Silicon DFT Engineer, Cloud Silicon
Dahl Consulting
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, path delay, and IDDQ) for Au
5d
Junior SoC DFT Engineer, Google Cloud
Dahl Consulting
Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bounda
5d
Senior Silicon DFT Engineer, Google Cloud
Dahl Consulting
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs. Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG). Work with other
6d
Junior Silicon DFT Engineer, Google Cloud
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bound
1w
Junior Silicon DFT Engineer, Google Cloud
Dahl Consulting
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Insert DFT logic, bound
1w
IP DFT Engineer
Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality. Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks. Inse
1w
SoC DFT Engineer, Google Cloud
Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, memory built-in self-test (MBIST), automatic test pattern generation (ATPG) and instrument/joint test action group (I/JTAG), and associated boot up and execution sequences. Complete al
Sunnyvale, CA, USA
hybrid
1w
Senior SOC DFT Engineer, Google Cloud
Dahl Consulting
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs. Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG). Work with other
1w
IP DFT Engineer
Dahl Consulting
Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality. Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks. Inse
1w
SoC DFT Engineer, Google Cloud
Dahl Consulting
Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, memory built-in self-test (MBIST), automatic test pattern generation (ATPG) and instrument/joint test action group (I/JTAG), and associated boot up and execution sequences. Complete al
Sunnyvale, CA, USA
hybrid
1w
Senior SOC DFT Engineer, Google Cloud
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs. Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG). Work with other
2w
Full Chip Front-End DFT Engineer
Dahl Consulting
Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits. Implement DFT logic, boundary scan, MBIST, scan chain